Principal VLSI/ASIC Verification Engineer
Hewlett Packard Enterprise is seeking a highly skilled and experienced Principal VLSI/ASIC Verification Engineer to join our dynamic team. As a Principal Engineer, you will play a crucial role in the development and verification of cutting-edge VLSI/ASIC designs for next-generation products. We are looking for individuals who possess exceptional technical expertise, a strong attention to detail, and a passion for pushing the boundaries of technology. If you are a self-motivated and driven professional with a proven track record in VLSI/ASIC verification, we want you to join our team and help drive innovation at HPE.
- Lead and drive the verification process for complex VLSI/ASIC designs for next-generation products.
- Develop and implement effective verification methodologies and strategies to ensure the quality and accuracy of the designs.
- Work closely with cross-functional teams, including design, architecture, and physical design teams, to ensure seamless integration of verification processes.
- Create and maintain detailed verification plans, including test cases, coverage metrics, and compliance with industry standards.
- Mentor and provide technical guidance to junior verification engineers, helping to develop their skills and knowledge.
- Stay updated with the latest industry trends and technologies related to VLSI/ASIC verification, and recommend improvements to existing processes.
- Identify and troubleshoot complex issues and provide innovative solutions to ensure timely delivery of high-quality designs.
- Collaborate with design and architecture teams to define and implement functional and performance verification requirements.
- Review and provide feedback on design specifications and participate in design reviews to ensure verification feasibility.
- Drive continuous improvement in the verification process by identifying and implementing automation and productivity enhancement opportunities.
Extensive Experience In Verification Methodologies: The Ideal Candidate Should Have At Least 8 Years Of Experience In Asic Verification, With A Strong Understanding Of Industry-Standard Verification Methodologies Such As Uvm And Ovm.
Expertise In Systemverilog And Verification Ip: The Candidate Should Possess A Deep Understanding Of Systemverilog And Have Hands-On Experience In Developing Complex Verification Environments Using Verification Ip.
Proficiency In Scripting Languages: Strong Knowledge Of Scripting Languages Such As Perl, Python, And Tcl Is Essential For Automating Various Verification Tasks And Streamlining The Verification Process.
Familiarity With Industry-Standard Tools: The Candidate Should Have Experience In Using Verification Tools Such As Questasim, Vcs, And Verdi For Simulation, Debugging, And Coverage Analysis.
Strong Problem-Solving Skills: The Candidate Should Possess Excellent Analytical And Problem-Solving Skills To Debug Complex Issues And Provide Effective Solutions To Meet Project Timelines. Experience In Debugging At The Gate Level Is Also Preferred.
Debugging
SystemVerilog
UVM
Asic Design
Formal Verification
Low Power
Functional Verification
Testbench Development
Assertion-Based Verification
Code Coverage
Vlsi Verification
Communication
Conflict Resolution
Emotional Intelligence
Leadership
Time management
creativity
Attention to detail
Teamwork
Adaptability
Problem-Solving
According to JobzMall, the average salary range for a Principal VLSI/ASIC Verification Engineer in Roseville, CA, USA is $150,000-$200,000 per year. This can vary depending on factors such as years of experience, education level, and the specific company or industry the engineer is working in. Salaries may also include bonuses, stock options, and other benefits.
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The Hewlett Packard Enterprise Company is an American multinational enterprise information technology company based in San Jose, California, founded on 1 November 2015 as part of splitting of the Hewlett-Packard company.
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