ASIC Design Verification Engineer

The ASIC Design Verification Engineer will work on verification of RTL functionality towards the development of Western Digital’s next generation eSSD SOC SSD controllers. Debugging Chip Level SoC RTL simulations to find functional bugs, working with the RTL design team to fix the bugs, reading design specs and developing/executing test plans. Use System Verilog/UVM, C++, and other methodologies to increase the rate at which ASIC bugs are located and resolved. Develop complex test cases that involve control/data paths of multiple IPs at module and chip level. Gate Level and FPGA RTL simulation environments.

According to JobzMall, the average salary range for a ASIC Design Verification Engineer in Milpitas, CA 95035, USA is $112,000 to $155,000 per year. This range can vary depending on the experience of the engineer, the company hiring the engineer, and the current state of the job market.

Western Digital Corporation is an American computer hard disk drive manufacturer and data storage company. It designs, manufactures and sells data technology products, including storage devices, data center systems and cloud storage services.