I am currently pursuing my Master degree at Arizona State Univeristy in Electrical Engineering with a specialization Analog and Mixed Signal Circuits.

Seeking opportunities in Digital Design, Physical Design, FPGA Engineer, Layout enginner, STA Engineer.

Arizona State University

Designed various low level RTL Designs in Verilog and verification via simulation in cadence.
● Synthesized the RTL code using Cadence RTL compiler and performed Automatic place & route using Cadence Encounter.
● Performed Floor planning, Power Planning, Pin Placement, Routing and Clock Tree Synthesis using cadence tools.

Vishal Jadhav

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