Senior Static Timing Analysis & Signoff Methodology Engineer

Welcome to NXP Semiconductors, a leading provider of secure connectivity solutions for embedded applications. We are currently seeking a highly skilled Senior Static Timing Analysis & Signoff Methodology Engineer to join our dynamic team. In this role, you will play a critical role in ensuring the timely and accurate signoff of our advanced semiconductor designs. We are looking for a detail-oriented and experienced professional who can thrive in a fast-paced and collaborative environment. If you have a strong background in static timing analysis and signoff methodology and are passionate about pushing the boundaries of semiconductor technology, we want to hear from you!

1. Perform static timing analysis (STA) of advanced semiconductor designs to ensure timing closure and signoff.
2. Develop and implement signoff methodologies for STA, including timing constraints, timing exceptions, and timing closure methodologies.
3. Collaborate with design teams to understand design requirements and provide guidance on timing constraints to meet performance targets.
4. Work closely with physical design teams to optimize timing and power constraints for efficient signoff.
5. Troubleshoot and resolve timing and methodology issues, providing recommendations for improvements and optimizations.
6. Stay current with industry trends and advancements in STA and signoff methodologies to continuously improve NXP's design flows.
7. Develop and maintain documentation for STA and signoff methodologies to ensure consistency and knowledge sharing across design teams.
8. Participate in cross-functional team meetings to provide updates on signoff status and collaborate on design challenges.
9. Mentor and train junior engineers on STA and signoff methodologies to build a strong and knowledgeable team.
10. Collaborate with third-party vendors and tool providers to evaluate and implement new tools and methodologies for STA and signoff.
11. Communicate effectively with project managers and stakeholders to provide updates on signoff progress and potential risks.
12. Work closely with the verification team to ensure accurate timing data and optimize timing constraints for accurate signoff.
13. Participate in design reviews and provide feedback on timing closure and signoff strategies.
14. Continuously look for opportunities to improve and optimize STA and signoff processes to increase efficiency and accuracy.

According to JobzMall, the average salary range for a Senior Static Timing Analysis & Signoff Methodology Engineer in Austin, TX, USA is $120,000 - $160,000 per year. This salary range can vary depending on factors such as the company, years of experience, and specific skills and certifications.

NXP Semiconductors Inc. is an Dutch semiconductor manufacturer, engages in the provision of secure connectivity solutions for embedded applications. It operates through the High Performance Mixed Signal and Standard Products segments. The High Performance Mixed Signal segment delivers high performance mixed signal solutions to customers to satisfy their system and sub-system needs across eight application areas: automotive, identification, mobile, consumer, computing, wireless infrastructure, lighting, and industrial.