SoC RTL Integration Engineer
Work with the chip architect and the SOC integration lead to understand architectural and interpret the design requirements. Work with the SoC integration lead and physical design team to create physical partitioning. Integrate sub-system IP into SOC via industry standard tools. Work with the verification team on a CI strategy that maximizes release velocity. Run quality checks and interpret SOC level failures; fix RTL failures. Maintain a CI/CD pipeline. Produce all collateral needed for physical design team and other design customers.
Strong fundamentals in digital ASIC design; experience using Verilog / System Verilog
5+ years of practical experience
Experience delivering RTL sub-systems and/or top level SOC RTL for multiple projects
Strong understanding of SoC integration challenges at subsystem and full chip level
Python
Perl
Power analysis
TCL
Time Management Skills
ASIC design implementation
Git / Azure DevOps
Design flows and methodologies
Process Improvement
Verbal communication
written communication
Adaptability
Problem-Solving
Detail Oriented and Organized
Multi tasker
According to JobzMall, the average salary range for a SoC RTL Integration Engineer in 8045 Arco Corporate Dr, Raleigh, NC 27617, USA is $80,000 to $120,000. This range may vary depending on the company, experience, and qualifications of the engineer.
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