
RTL Design Engineer
Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and IP for inclusion in subsystem designs. Participate in the development of Architecture and Microarchitecture specifications for the Logic components. Provide IP integration support to Subsystem customers and represents RTL team. Implement RTL in System Verilog, validating the design, synthesizing the design and closing timing. Work with specifications at multiple levels, including the HAS and MAS (microarchitecture spec). Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.
1+ year of experience in Logic design using System Verilog
Simulation and debug experience using VCS/Verdi experience
Documentation
Time Management Skills
Multiple clock domain design
FW development
Chassis2.0 and Chassis2.2
Speed path debugging skills
Process Improvement
Verbal communication
written communication
Adaptability
Problem Solving Skills
Detail oriented and highly organized
Multi tasker
According to JobzMall, the average salary range for a RTL Design Engineer in 1900 Prairie City Rd, Folsom, CA 95630, USA is between $84,000 and $107,000 per year. This range may vary depending on the qualifications and experience level of the candidate.
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Intel Corp. engages in the design, manufacture, and sale of computer products and technologies. It delivers computer, networking, and communications platforms. It operates its business through the following segments: Client Computing Group, Data Center Group, Internet of Things Group, Non-Volatile Memory Solutions Group, Intel Security Group, and Programmable Solutions.

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