
Physical Design Power Optimization Engineer
Are you a skilled and experienced engineer looking for a challenging and dynamic role? Do you have a passion for optimizing power consumption in high-performance chips? If so, we have an exciting opportunity for you! Intel is seeking a Physical Design Power Optimization Engineer to join our team and play a critical role in the development of cutting-edge technology. In this role, you will have the opportunity to work with a talented team and utilize your expertise to drive power optimization strategies for our next generation of products. If you have a strong background in physical design and power optimization, along with a drive for innovation and problem-solving, we'd love to hear from you!
- Collaborate with cross-functional teams to define and implement power optimization strategies for high-performance chips.
- Conduct thorough analysis of power consumption in existing designs and identify areas for improvement.
- Utilize industry-standard tools and techniques to optimize power usage in chip layout and physical design.
- Develop and implement innovative solutions to reduce power consumption while maintaining performance and functionality.
- Monitor and evaluate power optimization metrics and make adjustments as needed to meet project goals.
- Stay up-to-date with industry trends and advancements in power optimization techniques.
- Participate in design reviews and provide input on power optimization strategies.
- Troubleshoot and resolve any power-related issues in chip designs.
- Work closely with the verification team to ensure power optimization techniques are properly implemented and verified.
- Mentor and guide junior team members on power optimization best practices and techniques.
- Keep accurate documentation of power optimization processes and results.
- Collaborate with external partners and vendors to incorporate their power optimization solutions into our designs.
- Proactively identify potential risks and propose mitigation strategies related to power optimization.
- Communicate and present power optimization strategies and results to stakeholders and management.
- Continuously assess and improve power optimization methodologies and processes.
Bachelor's Degree In Electrical Engineering, Computer Engineering, Or Related Field.
Minimum Of 3 Years Of Experience In Physical Design And Power Optimization For Integrated Circuits.
Strong Understanding Of Power Distribution And Management Techniques In Digital And Analog Circuits.
Proficiency In Industry-Standard Design Tools Such As Cadence Virtuoso, Synopsys Ic Compiler, And Mentor Graphics Calibre.
Demonstrated Ability To Analyze And Optimize Power Consumption At Both The Block And Chip Level, As Well As Experience With Low-Power Design Methodologies.
Low power design
Power analysis
Floorplanning
Static Timing Analysis
Power
Clock Tree Synthesis
Clock Gating
Voltage Scaling
Power Grid Design
Power Budgeting
Power Reduction
Communication
Conflict Resolution
Emotional Intelligence
Leadership
Time management
creativity
Teamwork
Adaptability
Problem-Solving
Decision-making
According to JobzMall, the average salary range for a Physical Design Power Optimization Engineer in Austin, TX, USA is between $90,000 to $150,000 per year. This range can vary depending on factors such as the engineer's level of experience, the specific company they work for, and their skills and qualifications. Some senior engineers with more experience and specialized skills may earn higher salaries, while entry-level engineers may earn closer to the lower end of the range.
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Intel Corp. engages in the design, manufacture, and sale of computer products and technologies. It delivers computer, networking, and communications platforms. It operates its business through the following segments: Client Computing Group, Data Center Group, Internet of Things Group, Non-Volatile Memory Solutions Group, Intel Security Group, and Programmable Solutions.

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