
Verification Engineer
We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers. This is a rare opportunity to be part of an emerging product line, with market dominating products for a new line of devices. You will work with our worldwide design and architecture team, along with members of our Switch Team partners, to develop world class devices. All aspects of Design Verification, will be involved, along with opportunities for technical leadership.
A minimum of 8+ years of related experience
Preferable to have skills with SV and UVM, well versed in OOP
Need to have strong sense of teamwork and ability to work well with other.
Constrained random verification methodologies with experience driving completion via coverage closure.
Python
Perl
Time management competent
Verification methodologies
Verbal communication
written communication
Multitasking Skills
Adaptability
Problem-solving and resourcefulness
Strong organizational skills
Attention to detail and accuracy
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Broadcom Inc. is an American designer, developer, manufacturer and global supplier of a wide range of semiconductor and infrastructure software products, Broadcom's product portfolio serves the data center, networking, software, broadband, wireless, and storage and industrial markets.

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