R&D Engineer Hardware 5 CAD Digital Flow
Digital design and verification engineer in a mixed signal IP development group. Collaborate on developing specs for digital logic blocks. Write Verilog RTL based on specs. Set up and run synthesis, LINT/CDC checker, formal verification. Insert DFT in synthesis and check functional coverage. Debug DFT violations. Generate, verify and debug ATPG vectors. Work closely with DFT engineers from SOC teams. Create timing constraints, run timing analysis with Primetime and generate Extracted Timing Models (ETM).
Familiarity with processor microarchitectures and different IO bus protocols.
Hands on experience with Design Compiler, Primetime, Spyglass, formal verification tools, DFT tools (DFT Compiler, Tessent, etc.)
Familiar with lab equipment and analog/digital bench validation. Ability to debug and trouble-shoot chip issues.
Ability to work independently, strong debugging capabilities and good scripting skills.
System Verilog
Time management competent
Verilog RTL
Debugging and trouble-shoot chip issues
Good scripting skills
Run timing analysis
Verbal communication
written communication
Multitasking Skills
Adaptability
Problem-solving and resourcefulness
Strong organizational skills
Attention to detail and accuracy
According to JobzMall, the average salary range for a R&D Engineer Hardware 5 CAD Digital Flow in 1320 Ridder Park Dr, San Jose, CA 95131, USA is $117,000-$127,000 per year. This salary range is based on the most recent data from the Bureau of Labor Statistics and other sources.
Apply with Video Cover Letter Add a warm greeting to your application and stand out!
Broadcom Inc. is an American designer, developer, manufacturer and global supplier of a wide range of semiconductor and infrastructure software products, Broadcom's product portfolio serves the data center, networking, software, broadband, wireless, and storage and industrial markets.
Get interviewed today!
JobzMall is the world‘ s largest video talent marketplace.It‘s ultrafast, fun, and human.
Get Started