Design Engineer - STA / Timing Analysis

The candidate will design, implement, and deploy solutions mainly based on TCL, Python, Perl, and Unix shell. The candidate will also be running extensive and complex studies on digital circuits using industry standard SSTA tools and standard cell libraries with variation information. Experience in statistical data analysis, transistor level simulation, and script development in Unix is required. Experience in library characterization, timing signoff margin development, multi-foundry support, ASIC design flow such as physical implementation, timing closure, tape-out, and post-silicon analysis is a bonus. The candidate will have the opportunity to work closely with the experts in the fields of statistical static timing analysis, standard cell library timing and variation characterization and flow automation in a fast paced project oriented agile environment. Development will include writing scripts in TCL, Python, Perl, Unix shell and evaluation of new features and modeling techniques in STA tools.

According to JobzMall, the average salary range for a Design Engineer - STA / Timing Analysis in 1320 Ridder Park Dr, San Jose, CA 95131, USA is from $95,000 to $130,000 per year. This range is based on salary information for design engineers with similar skills and experience in the San Jose area.

The actual salary range for a Design Engineer - STA / Timing Analysis in 1320 Ridder Park Dr, San Jose, CA 95131, USA may differ depending on the individual's experience, skills, education level, and other factors.

Broadcom Inc. is an American designer, developer, manufacturer and global supplier of a wide range of semiconductor and infrastructure software products, Broadcom's product portfolio serves the data center, networking, software, broadband, wireless, and storage and industrial markets.