FPGA Verification Engineer

As an experienced Verification Engineer, you will have the opportunity to mentor junior engineers on SystemVerilog and the Verification Process in a fast growing organization. You will have the opportunity to be mentored by other FPGA Design and Verification Engineers in the Electronic Warfare domain knowledge. This is the opportunity to help innovate the way we use SystemVerilog/UVM. There are both opportunities to create new test environments almost from scratch and opportunities to improve on leveraged environments. This position is responsible for developing a configurable UVM testbench to simulate and verify complex VHDL FPGA designs that include ADC/DAC interfaces, DSP, and high speed SERDES. You will have the opportunity to drive the SystemVerilog/UVM methodology on a project.

According to JobzMall, the average salary range for a FPGA Verification Engineer in 450 Pulaski Rd, Greenlawn, NY 11740, USA is $100,000 - $120,000 per year. The salary range may vary depending on the experience and qualifications of the engineer.

BAE Systems plc, is an international defense, aerospace and security company which delivers a full range of products and services for air, land and naval forces, as well as advanced electronics, security, information technology solutions and customer support services.