
ASIC Design Verification Engineering
Accenture is looking for a highly motivated and experienced ASIC Design Verification Engineer to join our team. The successful candidate will be responsible for developing and executing verification plans to ensure chip designs meet their functional requirements. We are seeking a candidate with a strong background in ASIC design, verification, and validation.The ideal candidate for this role should possess excellent problem-solving skills, as well as the ability to work independently and collaboratively in a fast-paced environment. To be successful in this role, the candidate must be able to work with a diverse team of engineers in different disciplines. The successful candidate must also have a good understanding of industry standards and best practices in ASIC design, verification, and validation.The successful candidate must possess a Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, and at least 3 years of experience in ASIC design, verification, and validation. The candidate should also have working experience in Verilog, SystemVerilog, and UVM. Knowledge of scripting languages such as Perl, Python, and Tcl is preferred.The ASIC Design Verification Engineer must have excellent analytical and problem-solving skills, as well as excellent communication and interpersonal skills. The candidate must be organized and have the ability to work well under pressure. This position requires a self-starter who is driven and has the ability to effectively manage competing priorities. If you have the qualifications listed above and are looking for a challenging and rewarding role, then we encourage you to apply!
Systemverilog
Strong Knowledge Of Computer Architecture And Microprocessor Fundamentals
High-Level Asic Design And Verification Skills
In-Depth Experience With Asic Verification Methodologies Such As Vhdl/Verilog
Uvm/Ovm
Formal Verification
Experience With Scripting Languages Such As Python
Tcl
Perl
Familiarity With Verification Tools Such As Xilinx Vivado
Mentor Graphics Questa
Synopsys Vcs
Cadence Incisive
Documentation
Debugging
Scripting
Regression
SystemVerilog
UVM
Verilog
FPGA
ASIC
ModelSim
VCS
Coverage
Synthesis
Formal Verification
Verification Plan
Communication
Leadership
Time management
Interpersonal Skills
creativity
Organization
Critical thinking
Teamwork
Adaptability
Problem-Solving
According to JobzMall, the average salary range for a ASIC Design Verification Engineering in Montreal, QC, Canada is between CAD $86,154 and CAD $175,095 per year.
This salary range can vary depending on the experience of the engineer, the size and type of company they work for, and the specific responsibilities of the position. Generally, experienced ASIC Design Verification Engineers in the Montreal area can expect to make a salary in the upper end of the range.
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